A non-destructive channel stress characterization for gate-all-around nanosheet transistors by confocal Raman methodology

: Non-destructive stress characterization is essential for gate-all-around (GAA) nanosheet (NS) transistors technology, while it is a big challenge to be realized on nanometer-sized GAA devices by using traditional Micro-Raman spectroscopy due to its light spot far exceeding the device. In this work, a non-destructive stress characterization methodology of confocal Raman spectroscopy was proposed and performed for GAANS device fabrication. Channel stress evolution along the fabrication process was successfully characterized by designing high-density NS array and analyzing the linear scanned spectra in different structures. The related mechanism of stress evolution was systematically studied by Sentaurus process simulation. Ad-ditionally, applying this methodology on detecting the bending of suspended NS after channel release process was demonstrated. Therefore, this work might provide a promising solution to realize in-line characterization of channel stress in GAA NS transistors and process monitor of NS channel integrity.


INTRODUCTION
Strained silicon technology is one of the key technologies that has enabled the continued development of integrated circuits following Moore's Law since 90 nm process node [1,2].For 3 nm technology node and beyond, CMOS devices will change to a gate-all-around (GAA) structure, owing to its superior electrostatics and current driving capability compared to FinFET [3,4].For GAA NS transistors, the main transport surface orientation becomes (100)/ 110 , while the majority of conduction surface area is (110)/ 110 in FinFET where N/P current matching has been well realized.Because (100)/ 110 orientation has higher electron mobility but lower hole mobility, it is much more difficult to achieve N/P current matching for GAA NS transistors, which will require special engineering of channel stress.So far, characterization methods of channel stress on transistor level rely on transmission electron microscopes (TEM) which are of high precision but destructive [5].In order to efficiently engineer the channel stress for the research and devel-opment of device, an in-line measurement with real-time feedback would be essential for process and its integrity development.Therefore, a non-destructive, fast feedback, and accurate stress characterization will be highly preferred and expected for GAA NS transistors technology.
Raman spectroscopy is an optical characterization method with no damage to samples.It offers a wide range of molecular and material structural information through light interacting with the samples [6,7].In the early days, it was used to characterize global strain on wafer level, which was associated with epitaxial heterogeneous semiconductor materials [8][9][10][11][12].With sensitivity improvement of detection signal, the light spot size of Raman has been significantly reduced and Micro-Raman spectroscopy was developed for strain characterization on semiconductor devices level [13].In 2007, micro-Raman spectroscopy was applied to characterize the stress in patterned long Fins [14].Subsequently, micro-Raman spectroscopy was widely used to study the stress in micrometer-sized structures [15][16][17][18][19].With the semiconductor device approaching nanometer size, it is reported that there was no stress in vertically grown SiNWs [20,21].While stress is essential in GAA NS transistor fabricated by CMOS process [22], the stress characterization by Raman spectroscopy is of great potential, but has not been fully investigated yet.
In this work, a confocal Raman methodology was developed to characterize the channel stress in nanometer-sized GAA NS transistors.A short-loop experiment including several critical processes, i.e., Si/ Si 0.7 Ge 0.3 superlattice epitaxy, Fin pattern, channel release, and high-k/metal gate (HKMG) formation, was designed to explore and validate the capability of monitoring the stress evolution during the fabrication flow.The stress signals of NS were reinforced by creating high density NS array and analyzed by performing linear scanned spectra.Meanwhile, the detailed stress at each step during the fabrication process and the corresponding stress evolution mechanism were studied by Sentaurus process simulation.

EXPERIMENT
Figure 1 shows the schematic of the designed short-loop fabrication process of GAA NS transistor.As shown in Figure 1A, a superlattice structure of Si/Si 0.7 Ge 0.3 was epitaxially grown on bulk Si substrate with each layer of 10 nm confirmed by TEM.Then, electron-beam-lithography (EBL) was employed to define the Fin array with big pads at two terminals, and dry etching process by inductive coupled plasma (ICP) was performed to create the pattern as shown in Figure 1B.The Fins are 50 nm wide and 100 nm long from the top view SEM image.The Fin was oriented to 110 as X-direction. 110was defined as Y-direction and 001 as Z-direction.In Figure 1C, the Si 0.7 Ge 0.3 sacrificial layers were selectively removed through wet etching to release the Si NS [23] as shown in the tilted SEM image.Finally, 3 nm HfO 2 and 10 nm TiN were deposited by atomic layer deposition (ALD) to wrap around Si NS as HKMG with the associated TEM image as shown in Figure 1D.
The stress measurements were performed on a WITec alpha 300 R confocal Raman system equipped with a Zeiss microscope.The wavelength of the incident laser was 405 nm, whose penetration depth into Si was approximately 100 nm [24].The excitation laser was focused on the sample by a 100X objective lens (NA=0.9)with a beam spot size of approximately 300 nm.The laser power was kept under 10 mW to prevent sample heating.Raman spectra were obtained at room temperature in backscattering geometry from silicon (001) surface.

RESULTS AND DISCUSSION
Because the size of a single NS channel (100 nm×50 nm) is much smaller than the size of incident beam spot, it is difficult to directly obtain NS channel signal from the total measured signals.Therefore, specific structure with parallel connected high-density Fins was designed and fabricated to enhance the signal to noise ratio.Moreover, line-scanning measurement along Fin direction was implemented to be able to acquire a series of spectra from substrate, pads and Fins.As shown in Figure 2A, the main peaks located at 520 cm −1 were associated with Si-Si bond in Si material, including stacked Si layers and substrate.The intensity of these spectra in Fin region was the highest due to the edge-enhanced scattering effect [25], and decreased with the spot moving into pads and substrate region.The second peak around 510 cm −1 was associated with Si-Si bond stacked Si 0.7 Ge 0.3 layers.Besides, there was an asymmetry in the spectra of Fin region, in which the Si peak showed a broadening in the Fin region compared to that in other regions, indicating a possible strain in the Si-Fin layers.
In order to further understand the origin of the Si-Si peak broadening, another two samples: (1) the same structure on bulk Si substrate, and (2) structure with two pads only, were fabricated for comparative analysis.Similar line-scanning was performed and the spectra were shown in Figures 2B and 2C.The full width at half maxima (FWHM) of main Si-Si peak in different regions was extracted for all the three measured structures, as shown in Figure 2D.Obviously, a broadening of Si-Si main peak was only observed in Si/Si 0.7 Ge 0.3 Fin sample, while not in un-strained Si Fin and Si/Si 0.7 Ge 0.3 pad samples.This clearly tells that such broadening was not due to the edge signal from pads or Fin shaped bulk Si; it was the coupling of strained Si peak and unstrained Si substrate peak that caused the peak broadening phenomenon.In order to analyze the strain, further spectrum deconvolution by Lorentz fitting should be performed to track the Si-Si peak of strained Si layers.X-ray rocking curves (RCs) measurement was performed on Si/Si 0.7 Ge 0.3 stacked layers as shown in Figure 3A, to decide the Ge content and the strain status of Si 0.7 Ge 0.3 stacked layers.According to the RCs on (004) surface, the Ge content was calculated to be 29.9%, which was perfectly consistent with the designed value.The Kiessig Frings caused by the internal reflection of Si and Si 0.7 Ge 0.3 interface can be seen obviously, indicating that there was no strain relaxation in Si 0.7 Ge 0.3 layers.The period of superlattice was calculated to be 20.1 nm, which matched the TEM result in Figure 1A.The thickness of Si 0.7 Ge 0.3 layer in our sample was extracted to be 10 nm, which was less than the critical thickness of Si 0.7 Ge 0.3 , further demonstrating the Si 0.7 Ge 0.3 layers were fully strained [26].
The developed Raman characterization methodology was then applied on the channel stress measurement in each process step in order to characterize the stress evolution.The spectrum collected at each process step and its deconvolution were shown in Figure 3B.For the epitaxial Si/Si 0.7 Ge 0.3 superlattice wafer, Si-Si peaks of Si and Si 0.7 Ge 0.3 were located at 520.2 and 510.5 cm −1 , respectively.The position shift between these two peaks was used to calculate the strain in Si 0.7 Ge 0.3 layers [27]: Si-Si where ω Si−Si was the position of Si-Si peak of Si 0.7 Ge 0.3 , x was the Ge content (30%), and ε was the strain in Si 0.7 Ge 0.3 layer.The strain in Si 0.7 Ge 0.3 stacked layers was calculated to be −1.03% according to eq. (1).While there was no strained Si peak in the deconvolved spectra, indicating that the stacked Si layers were un- strained, that is, the original stress in Si NS channel of our device was zero.
In the following process steps of Fin pattern, channel release, and HKMG formation, the Si-Si peak of Si 0.7 Ge 0.3 at 510 cm −1 was primarily from the boundary of pad region.Its position did not shift during the fabrication process, indicating that there was no stress change in pads.The Si-Si peak associated with strained Si was extracted by Lorentz fitting at the position of 518.2, 523.6, and 522.7 cm −1 , respectively.This indicates that there is stress evolving along with the fabrication process.The position shift between strained Si-Si peak and substrate Si-Si peak was linearly correlated with stress and could be calculated by the equation as below [28]: where ω 0 was the position of substrate Si-Si peak and ω i was the position of strained Si-Si peak.p=−1.43ω0 2 and q=−1.89ω0 2 were the phonon deformation potentials (PDPs).S 11 =7.68×10 −12 Pa −1 and S 12 =2.14×10 −12 Pa −1 were the elastic constants of Si. σ XX , σ YY and σ ZZ were the stress component along the X, Y and Z directions, respectively.In our sample system, the stress was primarily in-plan and biaxial, and the component in Zdirection was too small and could be neglected.Therefore, eq. ( 2) could be simplified as By substituting the measured peak shift value in eq. ( 3), the σ XX +σ YY at different process step was calculated and shown in Figure 3C.At Fin pattern step, the stress in Si layers increased from zero to 0.87 GPa, indicating a tensile stress occurred in Si layers from blanket Si/Si 0.7 Ge 0.3 layers to Si/Si 0.7 Ge 0.3 Fin structure.During channel release, with the selective removing of Si 0.7 Ge 0.3 layers in Fin region, the Si layers were suspended as NS and the stress was changed from tensile to compressive, which will be beneficial to p-type GAA device.The compressive stress was reduced slightly and kept as −1.02 GPa after the following HKMG formation.
Moreover, a finite element modeling by Sentaurus process simulation has been calibrated with the modeling and experiment results in [5].The obtained stress components σ XX and σ YY were shown in the inset of Figure 3C; the corresponding σ XX +σ YY was plotted for comparison.The results from measurement and simulation matched very well.According to the simulation, the stress along the channel direction (σ XX ) was compressive, while σ YY was tensile at Fin pattern step and decreased to zero after channel release.
In order to further understand the mechanism of stress evolution, the stress distribution in channel and pad region was shown in Figure 3D.In Fin pattern process, the fully-strained Si 0.7 Ge 0.3 layers were partially relaxed due to the free face created by etching.As a result, the lattices of Si layers were stretched [5] which led to a tensile stress along Y-direction.Meanwhile, in X-direction, a compressive stress was generated due to the squeezing from two pads [29,30].At the following channel release step, the tensile stress in Si layers along Y-direction disappeared with the removing of Si 0.7 Ge 0.3 layers, but the compressive stress along Xdirection was enhanced due to further volume change.The squeezing from pads was completely applied on Si NS channels.Furthermore, the compressive stress σ XX was monotonically higher with narrower NS width, which should be considered for GAA devices design.
Besides the channel stress, the channel integrity was also critical in GAA technology.Bending or even worse, stiction, could possibly happen on the stacked Si NS channels during channel release step.The same Raman characterization and data analysis methodology were performed on bent stacked NS channels as seen in Figure 4A.Interestingly, an abnormal stress change was captured.Instead of compressive stress after channel release, an enhanced tensile stress was measured in bent stacked NS channels as shown in Figure 4B, which might be explained by the elastic deformation of stacked NS channels.This result indicates a potential application of this methodology on the characterization of stacked NS channels integrity.

CONCLUSION
In summary, a novel non-destructive channel stress measurement by confocal Raman methodology, which included special test structure design and measurement method of linear scanning, was proposed and performed on a GAA structure with vertically stacked NS channels.The Si NS channels stress evolution during the fabrication process was successfully characterized and well matched with the Sentaurus process simulation.The comprehensive analyses demonstrated the effectiveness of our proposed non-destructive Raman methodology to characterize the channel stress, which could be extended to real industrial GAA technology.Besides, the bent stacked NS channels were captured by an abnormal strain change compared to Sentaurus process simulation in channel release step.Therefore, this methodology might provide a promising approach to realizing in-line stress monitoring, and a determination of channel process health in the GAA manufacturing as well.

Figure 1
Figure 1 Schematic of a short-loop fabrication process flow of GAA NS transistor, including (A) epitaxy of Si/Si 0.7 Ge 0.3 superlattice on Si substrate, (B) Fin pattern, (C) channel release, and (D) HKMG formation.

Figure 2
Figure 2 Raman spectra extracted from different parts (substrate, pad and Fin) on (A) Si/Si 0.7 Ge 0.3 Fin, (B) bulk Si Fin, and (C) Si/Si 0.7 Ge 0.3 pads only.The line-scan was performed along the Fin direction.The full width at half maxima (FWHM) of Si-Si Raman peaks in Si along different parts were extracted and shown in (D).

Figure 3 (
Figure 3 (A) Measured rocking curves for the Si/Si 0.7 Ge 0.3 stacked layers on Si substrates on the (004) surface.(B) Raman spectra deconvolution by Lorentz fitting at different process steps with substrate Si peak located at 520.2 cm −1 .(C) The measured and simulated σ XX +σ YY stress evolution comparison along the fabrication process.The inset was the simulated stress components of σ XX and σ YY along X and Y directions.(D) σ XX and σ YY distribution in channel and pad regions.The section was along and perpendicular to the channel direction.

Figure 4 (
Figure 4 (A) Titled-view SEM image of bent stacked NS channels after NS release.(B) The measured and simulated stress evolution.A tensile stress enhancement appeared in measurement in contrast to a compressive stress in Sentaurus process simulation after channel release process.