© The Author(s) 2023. Published by China Science Publishing & Media Ltd. and EDP Sciences.

INTRODUCTION

In recent years, with the rapid development of artificial intelligence (AI) and deep learning, primary advances in computing power are required to complete massive computational tasks more efficiently [1]. Currently, computing systems are built based on the von Neumann architecture, where the processing unit and memory unit are separated. The latency associated with accessing data from the memory unit is the key performance bottleneck for the increasingly prominent AI related workloads [2]. In-memory computing is an alternative approach in which the memory units themselves are organized to process certain computational tasks [3,4]. The removal of data transmission between the processing unit and memory unit can significantly improve the computing performance and effectively avoid the energy cost of data transmission [5]. Various types of memory devices have been investigated for accomplishing in-memory computing, such as dynamic random-access memory (DRAM) [6–10], flash [11–13], resistive random-access memory (RRAM) [14–16], and phase change memory (PCM) [17,18]. Each memory device has key features for in-memory computing. Flash has the ability to implement multi-bit storage by applying different write voltages, but its endurance is relatively limited to ~10⁵ and requires a high write voltage. RRAM and PCM are based on an atomic rearrangement mechanism for conductance switching, which has a large resistance window to store multiple intermediate states [14,19]. It should be noted that the intermediate resistive state of the PCM drifts over time toward high resistance, and RRAM has problems with its electrical characteristics varying significantly not only between devices but also between programming cycles of the same device [3].

Theoretically, DRAM has almost unlimited cycling endurance (>10¹⁶), which allows for in situ training in neural networks [20]. However, conventional one-transistor-one-capacitor (1T1C) DRAM has a destructive read operation and is a type of binary memory [21], which limits the application of DRAM in the field of in-memory computing. The two-transistor-one-capacitor (2T1C) DRAM structure has been reported previously to fulfill the matrix-vector multiplication (MVM) operation in artificial neural networks (ANN), offering significant reduction in device area and energy consumption [22,23]. However, the conventional approach to achieving multi-bit operations typically involves employing several units that store binary weights through shift operations [24]. The distinct van der Waals characteristics of 2D materials enable us to achieve heterogeneous integration and exceptional device performance [25]. In this study, an alternative approach of utilizing a single unit for multi-bit storage and calculation was introduced. We demonstrated a heterogeneous integrated 2T1C DRAM device based on monolayer molybdenum disulfide (MoS₂) and graphene. The ultralow leakage current of the MoS₂ field-effect transistor (FET) permitted slow charge leakage, exhibiting a long retention time, and allowing for the retention of multi-level voltage in the 2T1C DRAM. The graphene transistor served as the readout terminal and performed a non-destructive readout of the voltage stored on the capacitor. The channel conductance of graphene transistors can be controlled by the gate voltage, enabling a linear adjustment of the output current. Additionally, the channel displays resistive characteristics that are linearly correlated with the source-drain voltage [26]. The outstanding linear output and transfer characteristics of graphene FET enabled the realization of multi-bit analog multiplication operation on a single unit.

RESULTS AND DISCUSSION

Figure 1A shows a schematic fabrication process of our 2T1C DRAM and an optical microscope image. The equivalent circuit diagram is shown in Figure 1B. The drain and gate terminals of the MoS₂ transistor (T₁) connect to the weight line voltage V_w and the refresh line voltage V_re, respectively. The source of T₁ connects to the bottom plate of the capacitor (C) and shares the potential with the back gate of the graphene transistor (T₂) simultaneously. The input voltage V_x is applied to the drain of T₂. The top-plate of C and the source of T₂ are grounded.

Figure 1 Structure of two-transistor-one-capacitor (2T1C) dynamic random-access memory (DRAM) cell and electrical characteristics of MoS2 and graphene transistors. (A) Schematic of our 2T1C DRAM cell fabrication process and optical microscope image of the fabricated device; scale bar: 100 μm. (B) Circuit diagram of 2T1C DRAM containing storage and calculation modules. (C) Transfer curve of the MoS2 field-effect transistor (FET). (D) Transfer and (E) output curves of the graphene FET.

Figure 1C presents the transfer curve of the MoS₂ FET. The gate voltage V_g varied from −3 to 3 V, and the applied drain-source voltage was 0.5 V. The MoS₂ FET exhibited a high current on/off ratio (10⁷) associated with its ultralow leakage current (156 fA/μm) at V_g = −3 V, which is correlated with a longer retention time of the DRAM and will be discussed later. On the other hand, the graphene FET exhibits a distinct bipolar behavior. As can be seen from the transfer curve of the graphene FET (Figure 1D), the Dirac point is located at V_g = −0.25 V with a current of 1.8 μA/μm, and a maximum current of 5.3 μA/μm was observed at V_g = 3 V. The transfer characteristics of the nine graphene transistors in the array were shown in Figure S1, demonstrating stable Dirac points and good device uniformity. Figure 1E presents the corresponding output characteristics of the graphene FET. Different from the saturation behavior observed in most MoS₂ FETs, the graphene FET shows ideal linearity in the range of 0 to 0.5 V, and the output curves can be clearly distinguished with V_g varying from 0 to 2 V. As shown in Figure S2, the dash lines are obtained by linear fitting of the transfer curve and the output curves with coefficients of determination R² as high as 0.990 and 0.9996, respectively. As V_g varied from 0 to 2 V, the conductance of the graphene transistor increases linearly from 0.6 to 1.3 mS. At low V_d (from 0 to 0.5 V), the channel of the graphene transistor exhibits a resistive characteristic and I_d has ideal linearity (see Supplementary information). Based on the C-V curves shown in Figure S3, the capacitance of the flat capacitor is 30 pF at a sweep frequency of 1 kHz. Furthermore, the parasitic capacitance of T₂ is only 1.4 pF, accounting for a mere 4.5% of the overall capacitance of the device.

To write data into the 2T1C DRAM, a V_w pulse with a width of 900 ms was input 50 ms earlier than the V_re pulse with a width of 800 ms, as shown in Figures 2A and 2B. During the programming operation, the pulse voltage of V_w was 2 V with a base level of 0 V. When V_re increased from −3 to 3 V, T₁ was switched to an on state, and the capacitor was charged to 2 V, the same as V_w. Then, V_re was set back to −3 V and T₁ was switched to the off state so that the charge in the capacitor could be retained. As shown in Figure 2C, V_c was 1.94 V when the V_re pulse was withdrawn (0 s). After holding for 9 s, V_c was at a high level of 1.8 V, corresponding to a voltage loss of only 7%. During the erasing operation, V_re was applied to turn on T₁ while V_w was maintained at 0 V, then the charge in the capacitor was erased and the voltage potential on the capacitor dropped to a low level. We also demonstrated the fast program/erase speed of T_program = 640 μs and T_erase = 650 μs as shown in Figure S4.

Figure 2 Dynamic programming and erasing operation. Input signals of Vre and Vw in (A) programming and (B) erasing operations. Retention characteristics (C) Vc and (D) Id over 9 s after programming/erasing operations. (E) Dynamic writing and reading by sequential programming and erasing pulses with 9 s interval.

The in situ readout of the data stored in the DRAM was realized with a fixed V_x of 0.5 V, and the output current of T₂ (I_d) is shown in Figure 3D. Since the non-ground terminal of the capacitor was connected to the gate of T₂, V_c also acted as the gate voltage of T₂. Under a programming state, V_c remained at a high voltage potential and I_d retained a high-current level (~4.8 μA/μm). Conversely, in the erased state, I_d retained a low-current level (~2.7 μA/μm). The ratio of the high current to the low current was 1.78 at the beginning and could be maintained at 1.70 after 9 s. The longest retention time of our 2T1C DRAM is 70 s with 10% drop in I_max corroborating the excellent retention performance as shown in Figure S4.

Figure 3 Characterization of the 2T1C unit cell. (A) Incremental step programming pulse (ISPP) waveform of Vw, varying from 0.5 to 2 V. Input pulse waveform of Vre. (B) Drain current Id of T2 with Vw varying from 0.5 to 2 V, where Vx = 0.1 V. (C) ISPP waveform applied to Vx, ranging from 0.1 to 0.4 V with 0.1 V increments. The pulse width was 0.1 s. (D) Corresponding Id curves when Vw was fixed at a series of values.

We then demonstrated a continuous writing and reading operation, as shown in Figure 2E. During the 100 s test period, the pulse width of the control signal V_re was 800 ms with a period interval of 10 s. V_w signal had a 2 V pulse with a 900 ms time width, with a period of 20 s. With a fixed V_x = 0.5 V, I_d can be switched between high and low current levels, corresponding to programmed and erased states, respectively. In contrast to the traditional silicon 1T1C DRAM, a destruction to the stored data during the reading operation can be avoided in our 2T1C MoS₂ DRAM, benefiting from such non-destructive readout characteristic. Thus our MoS₂ 2T1C structure circuit can realize a continuous non-destructive reading, which is more suitable for in-memory computing applications [27].

We then characterized the properties of the 2T1C storage module. Figure 3A shows the input pulse signals of V_w and V_re during the storage operation. T₁ was turned on by applying an active V_re (3 V), then V_w was applied to charge the capacitor. After the storage operation, T₁ was then turned off by applying a negative V_re (−3 V), and V_w was set to 0 V. Figure 3B shows the measured I_d-t curves, in which V_x was fixed at 0.1 V, and the V_w pulse increased from 0.5 to 2 V with a 0.5 V increment. Then, V_x was fixed for each I_d-t curve to monitor the current I_d over one period. After holding for 9 s, different I_d-t curves could still be clearly distinguished.

Thus, when V_w is stored in the capacitor as a weight value, it also controlled the channel conductance of T₂ as a gate input voltage. Thanks to the excellent linearity and wide current range in the graphene transistor T₂, it has a more distinguishable output than other nonlinear devices (Figures 1D and 1E), therefore our 2T1C DRAM could also realize multi-level storage and computing without complex linear modulation circuits [28]. Figure 3C shows a multi-step voltage waveform for V_x, which ranged from 0 to 0.4 V with a 50 mV increment and duration of 0.5 s. By applying such incremental step programming pulses (ISPPs) for V_x, Figure 3D shows I_d-t curves with five levels. Meanwhile, five levels of V_w were also applied from 0 to 2 V with an increment of 0.5 V, corresponding to the curves with different colors in Figure 3D. The above results can be summarized as, the output current I_d for different V_w values could be distinguished under the same V_x, and the current values for different V_x values could also be distinguished for the same V_w. The dynamic measurement for more than 2 bits was demonstrated in Figure S5. The results in Figure S5a showed that I_d is separated into 8 levels and can still be effectively distinguished after 9 s. This confirms that our device has the ability of 3-bit storage. The dynamic measurement results demonstrate that our 2T1C DRAM has the ability to realize 6 bits multiplication.

Multiplication is the most essential computational function in an FNN. Combining the long retention time of our 2T1C DRAM and the linear characteristic of T₂, in-memory multiplication can be implemented. We note that the current did not converge to zero when both the weight voltage V_w and the input voltage V_x were 0 V due to the intrinsic semimetallic behavior of the graphene whose conductance could not be completely turned off. Therefore, a current differential circuit was designed for the 2T1C DRAM, as shown in Figure 4A. The current I_d of T₂ is the input to the current differential module, which subtracts the differential current I₀ to obtain the output current I_out. The detailed circuit diagram of the current differential is shown on the lower left of Figure 4A. The current differential is composed of three parts, in which the red box is a current mirror to duplicate the input current (I_d = I′_d), while the transistors in the blue and green boxes (T₃ and T₄) are connected in parallel. The current differential circuit is heterogeneously integrated by two channel materials. The current mirror is composed of two MoS₂ transistors of the same size, while the graphene transistors T₃ and T₄ provide the differential current and output current, respectively. The same as T₂, and the drain of T₃ and T₄ are all connected to the input voltage V_x. The channel width-to-length ratio of T₃ is half that of T₂, and the gate of T₃ is connected to the gate of T₂ to ensure that T₃ and T₄ obtain the same drain-to-source voltage V_d as that of T₂ in the working range of V_w (from 0 to 2 V). T₄ is exactly equivalent to T₂, and its gate is applied with a voltage of 0 V to offer a differential current I₀ of the graphene transistor at V_g = 0 V. According to Kirchhoff’s current law, the output current through T₃ is I_out = I_d − I₀.

Figure 4 Implementation of multiplication operation. (A) Circuit diagram of current differential designed for the 2T1C DRAM. (B) Simulated Iout values as a function of the calculated Vw × Vx values. (C) Colormap of standard multiplication operation. (D) Colormap of Iout as a function of Vw and Vx.

Figure 4B shows the simulated I_out values as a function of their corresponding V_w × V_x values. I_out exhibited a linear dependence on V_w × V_x. We plotted the two-dimensional contour map of the standard multiplication operation (Z = X × Y) as shown in Figure 4C. The values of X and Y ranged from 0 to 0.5 and 0 to 2, respectively. The value of Z increased with the increase in X and Y, and it reached the maximum value at X = 2 and Y = 2. A two-dimensional colormap of I_out with different applied V_x and V_w values is shown in Figure 4D. The variation of Z with X and Y showed a practically identical trend to the variation of I_out with V_x and V_w. Thus, we have experimentally verified that the analog multiplication operation could be performed with our 2T1C DRAM. Taking advantage of the high on/off ratio of MoS₂ transistors (10⁷) and the linear output and transfer characteristics of graphene transistors described above, our 2T1C DRAM can simultaneously implement 2-bit memory with a retention time of more than 9 s as well as analog multiplication operations. Thus, in one retention period, the multiplication operations could be achieved by applying a set of short V_x pulses to the drain of the T₂ transistor, using the stored voltage V_w and the V_x pulses.

Thus, we have experimentally demonstrated long-time retention and the multi-bit storage capability of our 2T1C DRAM with non-destructive access, and the graphene transistor could be used to accomplish computing. Owing to the ideal cycling endurance of the DRAM structure, our 2T1C DRAM has the potential to be used for in situ training and recognition, rather than off-chip training, followed by mapping the weights to the device, which can significantly improve the recognition accuracy of the neural network. In addition, 2D layered semiconductors allow the stacking of materials with different properties together [29,30], which enables the monolithic integration of the 2T1C DRAM based on MoS₂ and graphene transistors. Therefore, our study supports the application of 2D layered semiconductors for future post-Moore applications.

Finally, we constructed a three-layer FNN to implement letter recognition. As shown in Figure 5A, the input layer contained 25 neurons corresponding to the gray values of 5 × 5 pixel images. The standard images of the letters to be recognized were “F,” “D,” and “U,” as shown on the left of Figure 5A. The input images of the FNN were obtained by adding 20% random noise to the standard gray values of the letters. The output layer contained three neurons corresponding to the output values of “F,” “D,” and “U,” and the hidden layer contained 9 neurons. The input and hidden layers were connected by 25 × 9 synapses denoted as a weight matrix . The hidden and output layers were connected by 9 × 3 synapses denoted as a weight matrix . Each synapse corresponded to one 2T1C DRAM cell, which consisted of five-level weights. The circuit diagram of our 2T1C DRAM simulating the m × n synapse array is shown in Figure 5B. This array stored an m × n weight matrix, which was written through bit lines under the control of refresh lines. The output current value of each line is

Figure 5 Fully connected neural network (FNN) for letter recognition. (A) Schematic diagram of FNN for letter recognition. The 5 × 5 pixel image of the letters “F,” “D,” and “U.” The grayscale values of the pixels were the inputs of the FNN. (B) Circuit diagram of an m × n array composed of 2T1C DRAM cells. (C) Recognition rate as a function of the training epochs. The inset shows the distribution of the 25 × 9 weights after 20 training epochs. (D) Colormaps of weights before and after training. These five-level weights represent the weight voltages Vw written to the 2T1C DRAM cells.

We then trained our simulation model with 1000 images, while another 1000 images were used as the test set. During the training process, the backpropagation algorithm was applied to train the model [31]. As shown in Figure 5C, the average recognition accuracy reached 84% within 20 training epochs. The weight values were quantized into 5 weight voltage levels which were the V_w written to the 2T1C DRAM. The inset of Figure 5C shows the weight voltages distribution of the 25 × 9 weights after 20 training epochs. Figure 5D shows a colormap of the weight voltages before and after training.

CONCLUSION

In conclusion, we utilized a 2T1C DRAM structure consisting of MoS₂ and graphene heterogeneous integration to accomplish a multi-bit voltage storage function. Owing to the low leakage current of the MoS₂ transistor, the stored electric charge could be retained for a long time, and meanwhile accurately modulate the conductance levels of the graphene transistor. Because of the linear characteristic of the graphene transistor’s output curve, analog multiplication could be successfully implemented. In contrast to the conventional 1T1C DRAM, our 2T1C DRAM could access the stored multi-bit information nondestructively. Finally, a 25 × 9 × 3 FNN was built based on our 2T1C DRAM, and the average recognition accuracy of the letters “F,” “D,” and “U” reached 84% within 20 training epochs. Considering the almost unlimited cycling endurance of DRAM, our 2T1C DRAM structure exhibits remarkable potential for in-memory computing.

METHODS

Device fabrication

As shown in Figure 1A, wafer-scale monolayer MoS₂ grown on a sapphire substrate using the chemical vapor deposition (CVD) method was used as the channel material of the T₁ transistor. The contact electrodes of T₁, the bottom plate of the capacitor, and the back gate of T₂ were patterned by photolithography, followed by depositing a 40 nm Au layer using electron beam evaporation (EBE). After this, the excess MoS₂ beyond the channel area was etched by inductively coupled plasma (ICP). A 16 nm HfO₂ high-k dielectric layer was grown by atomic layer deposition (ALD). The wafer-scale monolayer graphene grown by CVD was then transferred onto the dielectric layer as the channel of T₂. The 40 nm Au top gate electrode of T₁, the top plate of the capacitor, and the contact electrodes of T₂ were fabricated by photolithography and formed by resistive thermal evaporation.

Electrical measurements

All measurements were performed in an ambient environment at room temperature. The MoS₂ and graphene FETs were characterized using a semiconductor parameter analyzer (Agilent B1500A). For dynamic measurements and characterization of 2T1C DRAM cell, the Agilent B1500A was used to provide voltage signals and detect the output current. A waveform generator (Aligent 33260A) was also used to supply voltage waveforms to the test circuit, while an oscilloscope (DS 1054Z) was used for capturing output signal voltage.

Neural network implementation

In FNN simulation, the training process consisted of forward and backpropagation. The output values of the hidden layer are , where x_i is one of the pixel grayscale values of the input image, is the weight value between input neuron i and hidden neuron j, and refers to the bias of the hidden neuron. During backpropagation operation, the weight values between input layer and hidden layer were updated by , where the η=0.01, and is the calculated error.

Data availability

The original data are available from corresponding authors upon reasonable request.

Funding

This work was supported by the National Key Research and Development Program (2021YFA1200500), in part by the Innovation Program of Shanghai Municipal Education Commission (2021-01-07-00-07-E00077), and Shanghai Municipal Science and Technology Commission (21DZ1100900).

Author contributions

W.B., P.Z. and Y.X. initiated and supervised the project. S.G. and Y.W. designed the experiments and analyzed the data. X.D. contributed to the idea of the current differential circuit. X.W. and Q.S. were involved in device fabrications and electrical measurements. S.G. and Y.W. wrote the manuscript. All authors read and contributed to the manuscript revision.

Conflict of interest

The authors declare no conflict of interest.

Supplementary information

The supporting information is available online at https://doi.org/10.1360/nso/20220071. The supporting materials are published as submitted, without typesetting or editing. The responsibility for scientific accuracy and content remains entirely with the authors.

References

All Figures

Figure 1 Structure of two-transistor-one-capacitor (2T1C) dynamic random-access memory (DRAM) cell and electrical characteristics of MoS2 and graphene transistors. (A) Schematic of our 2T1C DRAM cell fabrication process and optical microscope image of the fabricated device; scale bar: 100 μm. (B) Circuit diagram of 2T1C DRAM containing storage and calculation modules. (C) Transfer curve of the MoS2 field-effect transistor (FET). (D) Transfer and (E) output curves of the graphene FET.

In the text

	Figure 2 Dynamic programming and erasing operation. Input signals of Vre and Vw in (A) programming and (B) erasing operations. Retention characteristics (C) Vc and (D) Id over 9 s after programming/erasing operations. (E) Dynamic writing and reading by sequential programming and erasing pulses with 9 s interval.
In the text

Figure 3 Characterization of the 2T1C unit cell. (A) Incremental step programming pulse (ISPP) waveform of Vw, varying from 0.5 to 2 V. Input pulse waveform of Vre. (B) Drain current Id of T2 with Vw varying from 0.5 to 2 V, where Vx = 0.1 V. (C) ISPP waveform applied to Vx, ranging from 0.1 to 0.4 V with 0.1 V increments. The pulse width was 0.1 s. (D) Corresponding Id curves when Vw was fixed at a series of values.

In the text

	Figure 4 Implementation of multiplication operation. (A) Circuit diagram of current differential designed for the 2T1C DRAM. (B) Simulated Iout values as a function of the calculated Vw × Vx values. (C) Colormap of standard multiplication operation. (D) Colormap of Iout as a function of Vw and Vx.
In the text

Figure 5 Fully connected neural network (FNN) for letter recognition. (A) Schematic diagram of FNN for letter recognition. The 5 × 5 pixel image of the letters “F,” “D,” and “U.” The grayscale values of the pixels were the inputs of the FNN. (B) Circuit diagram of an m × n array composed of 2T1C DRAM cells. (C) Recognition rate as a function of the training epochs. The inset shows the distribution of the 25 × 9 weights after 20 training epochs. (D) Colormaps of weights before and after training. These five-level weights represent the weight voltages Vw written to the 2T1C DRAM cells.

In the text